FIG. 1 is a block diagram showing a conventional image processing system of an IP CAM. The IP CAM image processing system comprises: an image-capturing module 10 and a rear-end image compression chip 14. The image-capturing module 10 further comprises a charge coupled device (CCD) and a digital signal processor (not shown).
When the CCD of the image-capturing module 10 is capturing an object, the capturing signals, generated by the CCD, is transmitted to the digital signal processor. The capturing signals are then transferred to pixel-format signals (i.e., resolution 720×480) by the digital signal processor. The digital signal processor then sequentially outputs an odd-field signal (resolution 720×240) and an even-field signal (resolution 720×240) according to the transferred pixel-format signals, wherein the odd-field signal is defined as the odd scanning lines of the CCD transmitted to the digital signal processor, and the even-field signal is defined as the even scanning lines of the CCD transmitted to the digital signal processor. The odd-field signal and the even-field signal derived from the image-capturing module 10 are then received and mixed to a complete frame (resolution 720×480) by the rear-end image compression chip 14 (i.e., MPEG-4/H.264 encoder). The generated frame is then further encoded and compressed by the rear-end image compression chip 14.
The above-mentioned process in the image processing system is further explained in detail through the image-capturing module 10 capturing a still object (resolution 10×8) depicted in FIG. 2. At time point t1, the capturing signals transmitted by the CCD are converted to a pixel-format signal by the digital signal processor, and the odd-field signal is generated by the digital signal processor. At time point t2, the capturing signals transmitted by the CCD are converted to a pixel-format signal by the digital signal processor, and the even-field signal is generated by the digital signal processor. FIG. 3A shows an odd-field signal (resolution 10×4), which is constituted by odd scanning lines (scanning lines 1, 3, 5, 7). FIG. 3B shows an even-field signal (resolution 10×4), which is constituted by even scanning lines (scanning lines 2, 4, 6, 8).
After the odd-field signal (resolution 10×4, depicted in FIG. 3A) and the even-field signal (resolution 10×4, depicted in FIG. 3B) are sequentially received by the rear-end image compression chip 14 at time point t1 and t2, respectively, the odd-field signal and the even-field signal are then mixed to a complete frame (resolution 10×8, depicted in FIG. 3C), and the rear-end image compression chip 14 further encodes and compresses the complete frame. Generally, the image-capturing module 10 outputs the odd-field signal and the even-field signal with the same frame rate of 30 frames per second (30 FPS).
However, if the object depicted in FIG. 2 is moving at a relatively high speed and is captured by the image-capturing module 10, a saw tooth type edge distortion may be resulted in due to each complete frame is mixed by two field signals. For example, an odd-field signal (resolution 10×4, depicted in FIG. 4A) is derived from the image-capturing module 10 at time point t1; and an even-field signal (resolution 10×4, depicted in FIG. 4B) is derived from the image-capturing module 10 at time point t2. Obviously, the saw tooth type edge distortion is occurred in the complete frame (resolution 10×8, depicted in FIG. 4C) if the odd-filed signal (depicted in FIG. 4A) and the even-field signal (depicted in FIG. 4B) are mixed (or interlaced) to a complete frame.
The saw tooth type edge distortion, resulted from an interlace CCD scanning a fast-moving object, can be avoided by introducing a 3D de-interlace chip in the image processing system. Instead of mixing the odd-filed signal and the even-field signal, the image processing system with the 3D de-interlace chip generates a complete frame through executing dynamic prediction compensation to each odd-filed signal and each even-field signal. In another word, when the odd-field signal (resolution 720×240) is generated at time point t1, the 3D de-interlace chip generates a complete frame (resolution 720×480) through executing the dynamic prediction compensation to the odd-field signal. Accordingly, when the even-field signal (resolution 720×240) is generated at time point t2, the 3D de-interlace chip generates another complete frame (resolution 720×480) through executing the dynamic prediction compensation to the even-field signal. Obviously, in the image processing system with the 3D de-interlace chip, not only the saw tooth type edge distortion resulted from the mixing procedure is avoided, but also the number of the generated frames is doubled.
Because the 3D de-interlace chip is originally designed for applying to LCDTV (Liquid Crystal Display TV) not for applying to the IP CAM, the output specification of the 3D de-interlace chip must be compatible of the input specification of the LCDTV. In another word, the 3D de-interlace chip is designed to output data with 16 bits data width and output data with a frame rate of 60 frames per second (60 FPS). However, the input specification of the rear-end image compression chip (i.e., MPEG-4/H.264 encoder) is designed to receive 8 bits data width and receives data with a frame rate of 30 frames per second (30 FPS). Therefore, designing an interface converting circuit for the compatibility between the 3D de-interlace chip and the rear-end image compression chip is the main purpose of the present invention.